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UCD4014B Datasheet
 
CMOS 8-STAGE STATIC SHIFT  REGISTERS


 
DESCRIPTION
 
The UTC UCD4014B is a 8-stage synchronous parallel or serial
input/serial output registers having common CLOCK and
PARALLEL/SERIAL CONTROL inputs, a SERIAL data input, and
individual parallel inputs to each register stage. Each register is a
D-type master-slave flip-flop. Q6, Q7, and Q8 are outputs. With the
positive clock line transition in the CD4014 parallel/serial entry is
made into the register synchronously.

In UCD4014 serial entry is controlled by the PARALLEL/SERIAL
CONTROL input. When the PARALLEL/SERIAL CONTROL input is
low, data is serially shifted into the 8-stage register synchronously with
the positive transition of the clock line. When the PARALLEL/SERIAL
CONTROL input is high, data is jammed into the 8-stage register via
the parallel input lines and synchronous with the positive transition of the clock line.
 
FEATURES
 
 
* Up to 20V operation voltage
* 12MHz (typ.) clock rate at 10V
* Maximum input current of 1μA at 18V
* Fully static operation
* 8 master-slave flip-flops plus output buffering and control gating
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