Press Center
Home About us Products Support Quality & Certification Career Contact us
• Power Management
    Linear Regulators
    Low Dropout Linear Regulators
    DDR Termination Regulators
    Shunt Reference Regulators
    Step Down Switching Regulators
    Switching Regulator
    Step-Up DC-DC Converter
    PWM Controller
    White LED Driver
    Supervisory Circuit
    Voltage Detection and System R
    USB Power Switch
    Power Factor Control
    Li-Battery Protection or Charg
    FET Bias Controllers
    Combo IC
    Inverting DC-DC Converter
• Amplifier / Comparator
    Audio Amplifiers
    Operational Amplifier
    Voltage Comparator
• Analog Switches
    Video Signal Switch
    Analog Multiplexers, Demultipl
• Hall ICs
• Special Application ICs
    Motor Controller IC
    Interface and Driver Circuit
    Telecommunication Circuit
    Melody IC
    Alarm /Sound Generator IC
    Remote Controller IC
    Television Circuit
    Leakage Current Detector
    Automotive IC
    A-D or D-A Converters
    Radio and Cassette Recorder Ci
    Mouse&Keyboard Controller
    Transient Voltage Suppressors
    Sense Monitor
    Video Filter
    ZCB snubber
• Logic
    Power Mosfet
• SCRs
Home >
UCD4015 Datasheet

cmos dual 4-stage static shift register
UCD4015 consists of two identical,independent,4-stage
serial-input/parallel-output registers. Each register has
independent CLOCK and RESET input as well as a single serial
DATA input. ”Q” outputs are available from each of the four
stages on both registers. All registers stages are D-type,
master-slave flip-flops. The logic level present at the DATA input
is transferred into the first register stage and shifted over one
stage at each positive-going clock transition. Resetting of all
stages is accomplished by a high level on the reset line. Register
expansion to 8 stages using one UCD4015 package or to more
than 8 stages using additional UCD4015’s is possible.
* 12MHz (typ.) clock rate at 10V
* Maximum input current of 1μA at 18V
* Fully static operation
* 8 master-slave flip-flops plus input and output buffering
About us  |  Products  |  Contact us
Copyright 2011 UTC All received