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Home > Timer
USA555 Datasheet

The UTC USA555 monolithic timing circuit is a highly stable
controller capable of producing accurate time delays or
oscillation. In the time-delay or monostable mode of operation,
the timed interval is controlled by a single external resistor and
capacitor network.  
In the astable mode of operation, the frequency and duty cycle
can be controlled independently with two external resistors and a
single external capacitor.
The threshold and trigger levels normally are two-thirds and
one-third, respectively, of VCC. These levels can be altered by use
of the control-voltage terminal. When the trigger input falls below
the trigger level, the flip-flop is set, and the output goes high. If
the trigger input is above the trigger level and the threshold input
is above the threshold level, the flip-flop is reset and the output is
low. The reset (RESET) input can override all other inputs and
can be used to initiate a new timing cycle. When RESET goes
low, the flip-flop is reset, and the output goes low. When the
output is low, a low-impedance path is provided between
discharge (DISCH) and ground.
The circuit may be triggered and reset on falling waveforms,
and the output structure can source or sink up to 200mA.
Operation is specified for supplies of 5V~15V.  
* Astable or monostable operation
* Low turn off time
* Operates in both astable and monostable modes
* Timing from microseconds to hours
* Adjustable duty cycle
* TTL-compatible output can sink or source up to 200Ma
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