DESCRIPTION

The UCA9617 enables I²C-bus  or SMBus translation down to

VCC(A) as low as 0.8V without degradation of system performance.

The UCA9617 contains two bidirectional open-drain buffers

specifically designed to support up-translation/down-translation

between the low voltage (as low as 0.8V) and a 2.5V, 3.3V or 5V

I²C-bus or SMBus. All inputs and I/Os are overvoltage tolerant to 5.5V

even when the device is unpowered (VCC(B) and/or VCC(A)=0V). Using

the UCA9617 enables the system designer to isolate two halves of a

bus for both voltage and capacitance. The SDA and SCL pins are

overvoltage tolerant and are high-impedance when the UCA9617 is

unpowered.

The UCA9617 includes a power-up circuit that keeps the output drivers turned off until VCC(B) is above 2.2V and

until after the internal reference circuits have settled ~ 400μs, and the VCC(A) is above 0.8V. VCC(B) and VCC(A) can

be applied in any sequence at power-up.

After power-up and with the enable (EN) HIGH, a LOW level on port A (below 0.3VCC(A)) turns the corresponding

port B driver (either SDA or SCL) on and drives port B down to about 0.55V. When port A rises above 0.3VCC(A), the

port B pull-down driver is turned off and the external pull-up resistor pulls the pin HIGH. When port B falls first and

goes below 0.4V, the port A driver is turned on and port A pulls down to ~ 0V. The port A pull-down is not enabled

unless the port B voltage goes below 0.4V.

 If the port B low voltage goes below 0.4V, the port B pull-down driver is enabled and port B will onl y be able to

rise to 0.55V until port A rises above 0.3VCC(A), then port B will continue to rise being pulled up by the external pull-up

resistor. The VCC(A) is only used to provide the 0.35VCC(A) reference to the port A input comparators and for the

power good detect circuit. The UCA9617 includes a VCC(A) overvoltage disable that turns the channel off if

0.4VCC(A)+0.8V>VCC(B). The UCA9617 logic and all I/Os are powered by the VCC(B) pin.

FEATURES

* Footprint and functional replacement for UCA9617 at

 Fast-mode speeds

* 2 channel, bidirectional buffer isolates capacitance and

allows 540pF on either side of the device at 1 MHz and

up to 4000pF at lower speeds

* Voltage level translation from 0.8V to 5.5V and from 2.2V

 to 5.5V

* Port A operating supply voltage range of 0.8V to 5.5V

 with normal levels

* Port B operating supply voltage range of 2.2V to 5.5V

 with static offset level

* 5V tolerant I²C-bus and enable pins

* 0Hz to 1000kHz clock frequency (the maximum system

 operating frequency may be less than 1000kHz because

 of the delays added by the repeater)

* Active HIGH repeater enable input referenced to VCC(B)

* Open-drain input/outputs

* Latching free operation

* Supports arbitration and clock stretching across the

 repeater

* Accommodates Standard-mode, Fast-mode and

 Fast-mode Plus I²C-bus devices, SMBus (standard and

 high power mode), PMBus and multiple masters

* Powered-off high-impedance I²C-bus pins