7−STAGE RIPPLE COUNTER  BINARY COUNTER / DIVIDERS

DESCRIPTION

The UTC UCD4024B is a 7−stage ripple counter with short

propagation delays and high maximum clock rates. The Reset input

has standard noise immunity, however the Clock input has

increased noise immunity due to Hysteresis. The output of each

counter stage is buffered.

FEATURES

* Diode Protection on All Inputs

* Output Transitions Occur on the Falling Edge of the Clock Pulse

* Supply Voltage Range = 3.0V to 18V

* Capable of Driving Two Low−power TTL Loads or On Low−power Schottky
  TTL Load Over the Rated Temperature Range