CMOS 8-STAGE SHIFT-AND-STORE BUS REGISTER

DESCRIPTION

The UCD4094 consists of an 8-stage shift register and 8-stage

D-type latch with 3-stage parallel outputs. Data is shifted serially

through the shift register on the positive going transition of the clock

input signal. The output of the last stage QS1 can be used to

cascade several devices.

The output of QS1 is transferred to a second output (QS2) on

the following negative transition of the clock input signal. The data of

each stage of the shift register is provided with a latch which latches

data on the negative going transition of the Strobe input signal.

When the strobe input is held high, data propagates through the

latch to a 3-state output buffer.

The buffer is enabled when Output Enable input is taken high.

FEATURES

* Operate from 3V to 18V

* Three-state outputs

* Standardized, symmetrical output characteristics

* 5V, 10V and 15V parametric ratings